1. Field of the Invention
This invention relates to a modulation method, a modulation apparatus, a demodulation method, a demodulation apparatus, an information recording medium, an information transmission method, and an information transmission apparatus.
2. Description of the Related Art
Some modulation (encoding) procedures used for digital signals recorded on recording mediums are of a (1, 7)RLL type, where “(1, 7)RLL” means run length limiting rules such that 1 to 7 successive bits of “0” should be between bits of “1” in a modulation-resultant bit stream. The (1, 7)RLL modulation tends to insufficiently suppress DC and near-DC components of a modulation-resultant bit stream. Therefore, in specified conditions, the spectrum of an information signal enters a frequency band assigned to a servo signal. In this case, the information signal interferes with servo control.
Japanese patent application publication number 6-195887/1994 discloses first and second modulation apparatuses.
The first modulation apparatus in Japanese application 6-195887 processes an input signal which has a sequence of symbols each having one byte. The first modulation apparatus includes an inverting circuit, a parallel-to-serial converting circuit, and a (1, 7)RLL modulation circuit. The inverting circuit receives the input signal, and inverts all bits in every odd-numbered symbol. The inverting circuit keeps every even-numbered symbol unchanged. The output signal from the inverting circuit is converted into a first bit stream by the parallel-to-serial converting circuit. The (1, 7)RLL modulation circuit subjects the first bit stream to (1, 7)RLL modulation, thereby generating a modulation-resultant bit stream (a second bit stream). The inversion of every odd-numbered symbol by the inverting circuit causes the suppression of a DC component of the modulation-resultant bit stream.
The second modulation apparatus in Japanese application 6-195887 includes a randomizing circuit and a (1, 7)RLL modulation circuit. The randomizing circuit receives an input signal, and randomizes the input signal. The randomizing circuit outputs the randomizing-resultant signal to the (1, 7)RLL modulation circuit. The (1, 7)RLL modulation circuit subjects the randomizing-resultant signal to (1, 7)RLL modulation, thereby generating a modulation-resultant bit stream. The signal processing by the randomizing circuit causes the suppression of a DC component of the modulation-resultant bit stream.
Japanese patent application publication number 10-340543/1998 discloses (1, 7)RLL modulation provided with DSV (digital sum variation) control for suppressing DC and low-frequency components of a modulation-resultant bit stream. According to the (1, 7)RLL modulation in Japanese application 10-340543, three successive bits in every prescribed position in a (1, 7)RLL code string is replaced by six successive DSV control bits of a pattern chosen so that the rules “(1, 7)RLL” will be observed.
Japanese patent application publication number 2000-105981 discloses (1, 8)RLL modulation provided with DSV control for suppressing DC and low-frequency components of a modulation-resultant bit stream. The (1, 8)RLL modulation in Japanese application 2000-105981 includes 8–12 modulation. The 8–12 modulation refers to a table containing 12-bit output code words assigned to 8-bit input code words respectively. Input data are divided into 8-bit segments each handled as an input code word. Every input code word is converted into an output code word by referring to the table. Specifically, the output code word assigned to the input code word is read out from the table. As a result, the input data are converted into a modulation-resultant bit stream formed by a sequence of output code words read out from the table. The output code words in the table and the output code words read out therefrom to form the modulation-resultant bit stream are designed so that the modulation-resultant bit stream will follow the rules “(1, 8)RLL”. Specifically, a succession of a preliminary current output code word and a next output code word is generated in response to every two successive input code words. Conditions of the connection between the preliminary current output code word and the next output code word are checked to decide whether or not the succession follows the rules “(1, 8)RLL”. When it is decided that the succession does not follow the rules “(1, 8)RLL”, the preliminary current output code word is replaced by another current output code word.
Japanese patent application publication number 2000-286709 discloses a modulation system which includes a formatter, an 8–15 modulator, and an NRZI converter. The formatter converts an input digital signal into a second digital signal of a predetermined format. The formatter outputs the second digital signal to the 8–15 modulator. The 8–15 modulator contains a set of seven different encoding tables. The 8–15 modulator converts or encodes every 8-bit block of the output digital signal from the formatter into a 15-bit code word by referring to the set of the encoding tables. The 15-bit code word forms a 15-bit block of a modulation-resultant bit stream (a modulation-resultant digital signal). The 15-bit code word is chosen to enable its NRZI conversion result to follow run length limiting rules such that a minimum run length is 3T and a maximum run length is 11T where T denotes the length or period of one bit (one channel bit). The 8–15 modulator outputs the modulation-resultant bit stream (the modulation-resultant digital signal) to the NRZI converter. The NRZI converter subjects the output digital signal of the 8–15 modulator to NRZI modulation, thereby generating a digital signal of an NRZI code.
In the modulation system of Japanese application 2000-286709, each of the encoding tables stores 15-bit code words assigned to different states of an 8-bit input block respectively. In addition, each of the encoding tables contains state information for selecting one from the encoding tables which will be used to convert a next 8-bit input block. This design is to enable the NRZI conversion result of a succession of two selected 15-bit code words to follow the run length limiting rules. The contents of the encoding tables are optimized in view of information about the frequencies of occurrence of different states of an 8-bit input block. Furthermore, first and second specified ones of the encoding tables are designed so that the NRZI modulation results of 15-bit code words in the first specified encoding table which correspond to prescribed 8-bit input blocks will be opposite in polarity (“odd-even” in the number of “1”) to those of 15-bit code words in the second specified encoding table.
In the modulation system of Japanese application 2000-286709, two candidate 15-bit code words may be selected from the first and second specified encoding tables in response to a given 8-bit input block. DSVs (digital sum variations) are calculated for the candidate 15-bit code words, respectively. The absolute values of the DSVs are compared. One of the candidate 15-bit code words which corresponds to the smaller of the absolute values of the DSVs is finally selected as a 15-bit output code word. In this way, DSV control is implemented.
Japanese patent application publication number 2000-332613 discloses a 4–6 modulator. The 4–6 modulator contains a set of four different encoding tables. The 4–6 modulator converts or encodes every 4-bit input code word into a 6-bit output code word by referring to the set of the encoding tables. The 6-bit output code word forms a 6-bit block of a modulation-resultant bit stream. Each of the encoding tables stores 6-bit output code words assigned to 4-bit input code words respectively. In addition, the encoding tables contain next-table selection numbers accompanying the respective 6-bit output code words therein. Each of the next-table selection numbers designates one among the encoding tables which will be used to convert a next 4-bit input code word. The output code words and the next-table selection numbers in the encoding tables are designed so that the modulation-resultant bit stream formed by a succession of selected output code words will follow (1, 7)RLL. First and second specified ones of the encoding tables are designed so that 6-bit output code words in the first specified encoding table which correspond to prescribed 4-bit input code words will be opposite in polarity (“odd-even” in the number of “1”) to those of 6-bit output code words in the second specified encoding table.
In the 4–6 modulator of Japanese application 2000-332613, two candidate 6-bit output code words may be selected from the first and second specified encoding tables in response to a given 4-bit input code word. DSVs (digital sum variations) are calculated for the candidate 6-bit output code words, respectively. The absolute values of the DSVs are compared. One of the candidate 6-bit output code words which corresponds to the smaller of the absolute values of the DSVs is selected as a final 6-bit output code word. In this way, DSV control is implemented.